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? freescale semiconductor, inc. , 2004-2006. all rights reserved. ? preliminary freescale semiconductor advance information mac7100ec rev. 1.2, 02/2006 this document contains information on a new product under development. freescale semiconductor reserves the right to change or discontinue this product without notice. table of contents 1 overview ................................................................. 1 2 ordering information ............................................... 2 3 electrical characteristics......................................... 4 3.1 parameter classification......................................4 3.2 absolute maximum ratings.................................4 3.3 esd protection and latch-up immunity ..............5 3.4 operating conditions...........................................6 3.5 input/output characteristics................................7 3.6 power dissipation and thermal characteristics..8 3.7 power supply ....................................................11 3.8 clock and reset generator ...............................15 3.9 external bus timing ..........................................20 3.10 analog-to-digital converter ...............................24 3.11 serial peripheral interface .................................29 3.12 flexcan interface .............................................32 3.13 common flash module .....................................32 4 device pin assignments ....................................... 36 4.1 mac7141 pin diagram......................................41 4.2 mac7142 pin diagram......................................42 4.3 mac7121 / mac7126 pin diagram ...................43 4.4 mac7122 pin diagram......................................44 4.5 mac7101 / mac7106 pin diagram ...................45 4.6 mac7111 / mac7116 pin diagram ...................46 4.7 mac7112 pin diagram......................................47 4.8 mac7131 pin diagram......................................48 4.9 mac7136 pin diagram......................................49 5 mechanical information......................................... 50 revision history ....................................................51 mac7100 microcontroller family hardware specifications covers mac7101, mac7106, mac7111, mac7116, mac7121, mac7126, mac7131, mac7136, mac7141 1 32-bit embedded controller division 1. with preliminary information on mac7112, mac7122, mac7142 devices. this document provides electrical specifications, pin assignments, and package diagrams for mac7100 family of microcontroller devices. for functional characteristics, refer to the mac7100 microcontroller family reference manual (mac7100rm). 1 overview the mac7100 family of microcontrollers (mcus) are members of a pin-compat ible family of 32-bit flash-memory-based devices developed specifically for embedded automotive applicat ions. the pin-compatible family concept enables users to select between different memory and peripheral options for scalable designs. all mac7100 family members are composed of a 32-bit arm7tdmi-s? central processi ng unit, up to 1 mbyte of embedded flash eeprom for program storage, up to 32 kbytes of embedded flash for data and/or program storage, and up to 48 kbytes of ram. the family is implemented with an enhanc ed dma (edma) controller to improve performance for transfers between memory and many of the on-chip peripherals. the peripheral set includes asynchronous serial communications interfaces (esci), serial peripheral interfaces (dspi), because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary ordering information freescale semiconductor 2 inter-integrated circuit (i 2 c?) bus controllers, flexcan interfaces , an enhanced modular i/o subsystem (emios), 10-bit analog-to-digital converter (atd ) module(s), general-purpos e timers (pit) and two special-purpose timers (rti and swt). the periphe rals share a large number of general purpose input-output (gpio) pins, all of which are bidirectional and available wi th interrupt capability to trigger wake-up from low-power chip modes. refer to table 2 for a comparison of family members and availability of peripheral modules on each device. the use of a pll allows power drai n and performance to be balanced to best fit requirements. the operating frequency of devices in the family is up to a maximum of 50 mhz. the internal data paths between the cpu core, edma, memory and periph erals are all 32 bits wi de, further improving performance for 32-bit applications. the mac7 111, mac7116, mac7131 and mac7136 also offer a 16-bit wide external data bus with 22 address lines. the family of de vices is capable of operating over a junction temperature range of ?40 c to 150 c. 2 ordering information figure 1. order part number example the mask set of a device is marked with a four-charact er code consisting of a le tter, two numerical digits, and a letter, for example l49p. slight variations to the mask set identification code may result in an optional numerical digi t preceding the standard four-cha racter code, for example 0l49p. table 1. mac7100 family mask set to part number correspondence mask set status part number(s) 0l49p engineering samples pac7101, pac7111, pac7121, pac7131, pac7141 1l49p limited production, pre-qua lification pac7101, pac7111, pac7121, pac7131, pac7141 0l47w limited production, pre-qua lification pac7101, pac7111, pac7121, pac7131, pac7141 1l47w fully-qualified, production mac7101, mac7111, mac7121, mac7131, mac7141 0l61w engineering samples pac7112, pac7122, pac7142 0l38y engineering samples pac7106, pac7116, pac7126, pac7136 1l38y fully-qualified, production mac7106, mac7116, mac7126, mac7136 m ac 7 1 0 1 c pv 50 xx qualification status core code core number generation / family package option device number temperature range package identifier speed (mhz) optional package identifiers temperature option c = ?40 c to 85 c v = ?40 c to105 c m = ?40 c to125 c package option fu = 100 lqfp af = 100 lqfp, rohs pv = 112 / 144 lqfp ag = 112 / 144 lqfp, rohs vf = 208 map bga vm = 208 map bga, rohs because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
ordering information mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 3 table 2. mac7100 family device derivatives module options mac7101 mac7111 mac7121 mac7131 mac7141 mac7112 mac7122 mac7142 mac7106 mac7116 mac7126 mac7136 program flash 512 kbytes 256 kbytes 1 mbyte data flash 32 kbytes sram 32 kbytes 16 kbytes 48 kbytes external bus ?yes?yes?????yes?yes atd modules 1 notes: 1. 16 channels, 8/10-bit, per module. a ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s byes??yes????yes??yes can modules a ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s b yes yes yes yes yes yes yes yes yes yes yes yes c ye s ye s ye s ye s ? ? ? ? ye s ye s ye s ye s dyesyesyesyes????yesyesyesyes esci modules a ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s b yes yes yes yes yes yes yes yes yes yes yes yes c ye s ye s ye s ye s ? ye s ye s ? ye s ye s ye s ye s d yes yes yes yes yes ? ? ? yes yes yes yes dspi modules a ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s 2 2. four additional chip selects available. byes yes ye s 3 3. pb11 / pcs2_b not available on non-l49p-mask devices; pb10 / pcs5_b / pcss_b not available on mask l47w devices. ye s ye s ye s ye s 3 ye s ye s ye s ye s 3 ye s 2 i 2 c module ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s emios module 16 channels, 16-bit timer module 10 channels, 24-bit general-purpose i/o ports/pins a10161016 41610 410161016 b 16 16 15 16 16 16 15 16 16 16 15 16 c1216 116?16 1?1216 116 d 10 4 4. reduce these values by one for mask set l49p devices (pd2 is not available for general-purpose use). 16 4 11 4 16 4 10 4 16 11 10 10 16 11 16 e161616161616161616161616 f 16 16 16 16 16 16 16 16 16 16 16 16 g161616161016161016161616 h 16 ? ? 16 ? ? ? ? 16 ? ? 16 i???????????16 total (max.) 112 4 112 4 85 4 128 4 72 4 112 85 72 112 112 85 144 package 144 lqfp 144 lqfp 112 lqfp 208 bga 100 lqfp 144 lqfp 112 lqfp 100 lqfp 144 lqfp 144 lqfp 112 lqfp 208 bga because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains electrical information for ma c7100 family microcontroll ers. the information is preliminary and subject to change without notice. mac7100 family devices are specified and tested over the 5 v and 3.3 v ranges. for operation at any voltage within that range, the 3.3 v specifications ge nerally apply. however, no production testin g is done to verify operation at interm ediate supply voltage levels. 3.1 parameter classification the electrical parameters shown in this appendix are derived by various met hods. to provide a better understanding to the designer, the fo llowing classification is used. parameters are tagged accordingly in the column labeled ?c? of the parametric tables, as appropriate. 3.2 absolute maximum ratings absolute maximum ratings are stress ratings only. functional operation outside these maximums is not guaranteed. stress beyond these limits may affect reliability or cause permanent damage to the device. mac7100 family devices contain circuitry protecting agai nst damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. re liability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either v ss 5 1 or v dd 5 1 ). table 3. parametric value classification p parameters guaranteed during production testing on each individual device. c parameters derived by the design characterization and by measuring a statistically relevant sample size across process variations. t parameters derived by design characterization on a small sa mple size from typical devi ces under typical conditions (unless otherwise noted). all values shown in the typical co lumn are within this classification, even if not so tagged. d parameters derived mainly from simulations. 1. refer to section 3.7, ?power supply,? for definition of v ss 5 and v dd 5. table 4. absolute maximum ratings num rating symbol min max unit a1a i/o drivers supply voltage v dd x?0.3 +6.0v a2 digital logic supply voltage 1 v dd 2.5 ?0.3 +3.0 v a3 pll supply voltage 1 v dd pll ?0.3 +3.0 v a4 analog supply voltage v dd a?0.3 +6.0v a5 analog reference v rh, v rl ?0.3 +6.0 v a6 voltage difference v dd x to v dd a vddx ?0.3 +0.3 v a7 voltage difference v ss x to v ss a vssx ?0.3 +0.3 v a8 voltage difference v rh ? v rl v rh ? v rl ?0.3 +6.0 v because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 5 3.3 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qua lification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model ( mm) and the charge device model. a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is perf ormed per the applicable device specification at room temperature followed by hot temperature, unle ss specified otherwise. a9 voltage difference v dd a ? v rh v dd a ? v rh ?0.3 +6.0 v a10 digital i/o input voltage v in ?0.3 +6.0 v a11 xfc, extal, xtal inputs v ilv ?0.3 +3.0 v a12 test input v test ?0.3 ? 2 v instantaneous maximum current 3 a13 single pin limit for xfc, extal, xtal 4 i dl ?25 +25 ma a14 single pin limit for all digital i/o pins 5 i d ?25 +25 ma a15 single pin limit for all analog input pins 5 i da ?25 +25 ma a16 single pin limit for test 2 i dt ?0.25 0 ma a17 storage temperature range t stg ?65 +155 c notes: 1. the device contains an internal voltage regulator to generate the logic and pll supply from the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. 2. this pin is clamped low to v ss x, but not clamped high, and must be tied low in applications. 3. input must be current limi ted to the value specified. to determine the value of the required current-limiting resistor, use the larger of the calculated values using v posclamp = v dd a + 0.3v and v negclamp = ?0.3 v. 4. these pins are internally clamped to v ss pll and v dd pll. 5. all i/o pins are internally clamped to v ss x and v dd x, v ss r and v dd r or v ss a and v dd a. table 5. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulses per pin positive negative ?? 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative ?? 3 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table 4. absolute maximum ratings (continued) num rating symbol min max unit because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 6 3.4 operating conditions unless otherwise noted, the following conditions apply to all parametric data. refer to the temperature rating of the device (c, v, m) with respect to ambient temperature (t a ) and junction temperature (t j ). for power dissipation calculations refer to section 3.6, ?power dissipation and thermal characteristics.? 3.4.1 input/output pins the i/o pins operate at a nominal level of 3.3 v to 5 v. this class of pins is comp rised of the clocks, control and general purpose/peripheral pins. th e internal structure of these pins is identical; however, some functionality may be disabled (for example, for analog inputs th e output drivers, pul l-up/down resistors are permanently disabled). table 6. esd and latch-up protection characteristics num c rating symbol min max unit b1 c human body model (hbm) v hbm 2000 ? v b2 c machine model (mm) v mm 200 ? v b3 c charge device model (cdm) v cdm 500 ? v b4 c latch-up current at t a = 125 c positive negative i lat +100 ?100 ? ma b5 c latch-up current at t a = 27 c positive negative i lat +200 ?200 ?ma table 7. mac7100 family device operating conditions num rating symbol min typ max unit c1 i/o drivers supply voltage v dd x3.15 5 5.5 v c2 digital logic supply voltage 1 notes: 1. these ratings apply only when the vreg is disabled and the device is powered from an external source. v dd 2.5 2.35 2.5 2.75 v c3 pll supply voltage 1 v dd pll 2.35 2.5 2.75 v c4 analog supply voltage v dd a3.15 5 5.5 v c5 voltage difference v dd x to v dd a vdd x ?0.1 0 0.1 v c6 voltage difference v ss x to v ss a vss x ?0.1 0 0.1 v c7 oscillator frequency f osc 2 2. throughout this document, t osc refers to 1 f osc , and t sys refers to 1 f sys . 0.5 ? 16 mhz c8 system clock frequency f sys 2 0.5 ? 50 mhz c9a mac71xxc operating junction temperature range 3 3. refer to section 3.6, ?power dissipation and thermal characteristics,? for more details about the relation between ambient temperature t a and device junction temperature t j . t j ?40 ? 110 c c9b operating ambient temperature range 3 t a ?40 25 85 c c10a mac71xxv operating junction temperature range 3 t j ?40 ? 130 c c10b operating ambient temperature range 3 t a ?4025105 c c11a mac71xxm operating junction temperature range 3 t j ?40 ? 150 c c11b operating ambient temperature range 3 t a ?4025125 c because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 7 3.4.2 oscillator pins the pins xfc, extal, xtal are dedicated to the os cillator and operate at a nominal level of 2.5v. 3.5 input/output characteristics this section describes the character istics of all i/o pins in both 3. 3 v and 5 v operating conditions. all parameters are not always applicable; for exampl e, not all pins feature pull up/down resistances. table 8. 5.0 v i/o characteristics conditions shown in ta b l e 7 unless otherwise noted num c rating symbol min typ max unit d1a p input high voltage v ih 0.65 v dd 5 1 notes: 1. refer to section 3.7, ?power supply,? for definition of v ss 5 and v dd 5. ?? v d1b t input high voltage v ih ??v dd 5 + 0.3 1 v d2a p input low voltage v il ? ? 0.35 v dd 5 1 v d2b t input low voltage v il v ss 5 ? 0.3 1 ?? v d3 c input hysteresis v hys ?250?mv d4 p input leakage current (pins in high impedance input mode) v in = v dd 5 or v ss 5 1 i in ?1 2 2. maximum leakage current occurs at maximum operating te mperature. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. ?1 2 a d5 p output high voltage (pins in output mode) partial drive i oh = ?2ma full drive i oh = ?10ma v oh v dd 5 ? 0.8 ?? v d6 p output low voltage (pins in output mode) partial drive i ol = +2ma full drive i ol = +10ma v ol ??0.8v d7 p internal pull up device current, tested at v il max. i pul ? ? ?130 a d8 p internal pull up device current, tested at v ih min. i puh ?10 ? ? a d9 p internal pull down device current, tested at v ih min. i pdh ??130 a d10 p internal pull down device current, tested at v il max. i pdl 10 ? ? a d11 d input capacitance c in ?6?pf d12 t injection current 3 single pin limit total device limit. sum of all injected currents 3. refer to section 3.7.1, ?current injection,? for more details i ics i icp ?2.5 ?25 ? 2.5 25 ma d13 p port interrupt input pulse filtered 4 4. parameter only applies in stop or pseudo stop mode. t pulse ?? 3 s d14 p port interrupt input pulse passed 4 t pulse 10 ? ? s because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 8 3.6 power dissipation and thermal characteristics power dissipation and thermal characteristics are closel y related. the user must assure that the maximum operating junction temperature is not exceeded. table 9. 3.3 v i/o characteristics conditions shown in ta bl e 7 , with v dd x = 3.3 v ?5%/+10% and a temperature maximum of +140 c unless otherwise noted. num c rating symbol min typ max unit e1a p input high voltage v ih 0.65 v dd 5 1 notes: 1. refer to section 3.7, ?power supply,? for definition of v ss 5 and v dd 5. ?? v e1b t input high voltage v ih ??v dd 5 + 0.3 1 v e2a p input low voltage v il ? ? 0.35 v dd 5 1 v e2b t input low voltage v il v ss 5 ? 0.3 1 ?? v e3 c input hysteresis v hys ?250?mv e4 p input leakage current (pins in high impedance input mode) v in = v dd 5 or v ss 5 1 i in ?1 2 2. maximum leakage current occurs at maximum operating te mperature. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. ?1 2 a e5 p output high voltage (pins in output mode) partial drive i oh = ?0.75ma full drive i oh = ?4.5ma v oh v dd 5 ? 0.4 ?? v e6 p output low voltage (pins in output mode) partial drive i ol = +0.9ma full drive i ol = +5.5ma v ol ??0.4v e7 p internal pull up device current, tested at v il max. i pul ? ? ?60 a e8 p internal pull up device current, tested at v ih min. i puh ?6 ? ? a e9 p internal pull down device current, tested at v ih min. i pdh ??60 a e10 p internal pull down device current, tested at v il max. i pdl 6?? a e11 d input capacitance c in ?6?pf e12 t injection current 3 single pin limit total device limit. sum of all injected currents 3. refer to section 3.7.1, ?current injection,? for more details i ics i icp ?2.5 ?25 ? 2.5 25 ma e13 p port interrupt input pulse filtered 4 4. parameter only applies in stop or pseudo stop mode. t pulse ?? 3 s e14 p port interrupt input pulse passed 4 t pulse 10 ? ? s because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 9 note that the jedec specification reserves the symbol r ja or ja (theta-ja) strictly for junction-to- ambient thermal resistance on a 1s test bo ard in natural convection environment. r jma or jma (theta-jma) will be used for both junction-to-ambient on a 2s2p test boa rd in natural convection and for junction-to-ambient with forced c onvection on both 1s and 2s2p test boar ds. it is anticipated that the generic name, ja , will continue to be commonly used. the average chip-junction temperature (t j ) in c is obtained from the formula: eqn. 1 where the total power dissipation is calculated as: eqn. 2 where two cases must be considered for p int : 1. internal voltage regulator enabled: eqn. 3 2. internal voltage regulator disabled (v dd r = v ss r = system ground): eqn. 4 p io is the sum of all output currents on input/output pins associated with v dd x: eqn. 5 where eqn. 6 or eqn. 7 table 10. thermal resistance 1/8 simulation model packaging parameters component conductivity mold compound 0.9 w/m k leadframe (copper) 263 w/m k die attach 1.7 w/m k t j t a p d ja ? += t j junction temperature ( c) = t a ambient temperature ( c) = p d total chip power dissipation (w) = ja package thermal resistance ( c/w) = p d p int p io += p int chip internal power dissipation (w) = p io input / output power dissipation (w) = p int i dd rv dd r () i dd av dd a () + = p int i dd 2.5 v dd 2.5 () i dd pll v dd pll () i dd av dd a () ++ = p io r dson i i io i () 2 ? = r dson v ol i ol --------- (for outputs driven low) = r dson v dd xv oh ? i ol ------------------------------ - (for outputs driven high) = because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 10 3.6.1 thermal resistance simulation details comments: 1. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with t he board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board at the center lead. for fused lead packages, the adjacent lead is used. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) . 6. thermal characterization parameter indicating the temperatur e difference between package top and junction temperature per jed ec jesd51-2. when greek letters are not available, the ther mal characterization paramet er is written as psi-jt. table 11. thermal resistance for case outline 983?02, 100 lead 14x14 mm lqfp, 0.5 mm pitch rating environment symbol value unit comments junction to ambient (natural convection) single layer board (1s) r ja 44 c/w 1 , 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1 , 3 junction to ambient (@ 200 ft./min.) single layer board (1s) r jma 37 c/w 1 , 3 junction to ambient (@ 200 ft./min.) four layer board (2s2p) r jma 29 c/w 1 , 3 junction to board r jb 18 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 12. thermal resistance for case outline 987?01, 112 lead 20x20 mm lqfp, 0.65 mm pitch rating environment symbol value unit comments junction to ambient (natural convection) single layer board (1s) r ja 42 c/w 1 , 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) single layer board (1s) r jma 35 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) four layer board (2s2p) r jma 30 c/w 1 , 3 junction to board r jb 22 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 13. thermal resistance for case outline 918?03, 144 lead 20x20 mm lqfp, 0.5 mm pitch rating environment symbol value unit comments junction to ambient (natural convection) single layer board (1s) r ja 42 c/w 1 , 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) single layer board (1s) r jma 35 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) four layer board (2s2p) r jma 30 c/w 1 , 3 junction to board r jb 22 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 14. thermal resistance for case outline 1159a-01, 208 lead 17x17 mm map bga, 1.0 mm pitch rating environment symbol value unit comments junction to ambient (natural convection) single layer board (1s) r ja 46 c/w 1 , 2 junction to ambient (natural convection) four layer board (2s2p) r jma 29 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) single layer board (1s) r jma 38 c/w 1 , 3 junction to ambient (@ 200 ft. /min.) four layer board (2s2p) r jma 26 c/w 1 , 3 junction to board r jb 19 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 11 3.7 power supply the mac71xx family utilizes several pins to supply power to the oscill ator, pll, digital core, i/o ports and atd. in the context of this section, v dd 5 is used for v dd a, v dd r or v dd x; v ss 5 is used for v ss a, v ss r or v ss x unless otherwise noted. i dd 5 denotes the sum of the currents flowing into the v dd a, v dd x, and v dd r. v dd is used for v dd 2.5, and v dd pll, v ss is used for v ss 2.5 and v ss pll. i dd is used for the sum of the currents flowing into v dd 2.5 and v dd pll. 3.7.1 current injection the power supply must maintain regulation within the v dd 5 or v dd 2.5 operating range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd 5) is greater than i dd 5, the injection curren t may flow out of v dd 5 and could result in the external power supply going out of regulation. it is important to ensure that the external v dd 5 load will shunt cu rrent greater than the maximum injection current. the greatest risk will be when the mcu is consuming very little power (for example, if no system clock is presen t, or if the clock rate is very low). 3.7.2 power supply pins the v dd r ? v ss r pair supplies the internal voltage regulator. the v dd a ? v ss a pair supplies the a/d converter and the referen ce circuit of the internal voltage regulator. the v dd x ? v ss x pair supplies the i/o pins. v dd pll ? v ss pll pair supplies the oscillator and pll. all v dd x pins are internally connected by metal. all v ss x pins are internally connected by metal. all v ss 2.5 pins are internally connected by metal. v dd a, v dd x and v dd r as well as v ss a, v ss x and v ss r are connected by anti-parallel diodes for esd protection. 3.7.3 supply current characteristics table 15 and table 16 list supply current characteristics for mac71 x 1 and mac71 x 6 devices at 40 mhz and 50 mhz operation, respectively. characteristics for mac71 x 2 devices are to be determined (tbd). all current measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enable d at the specified system frequency, using a 4 mhz oscillator in low power mode. production testing is performed using a square wave signal at the extal input. in expanded modes, the currents are highly de pendent on the load and duty cycle on the address, data and control signals, thus no general numbers can be gi ven. a good estimate is to take the single chip currents and add the currents due to the external loads. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 12 table 15. mac71 x 1/6 1 device supply current characteristics ? 40 mhz notes: 1. mac71 x 2 characteristics are to be determined (tbd). conditions shown in ta b l e 7 , with f sys = 40 mhz. num c rating symbol typ max unit f1 p run supply current, single chip i dd r reg 100 130 ma f2 c doze supply current i dd d reg run doze pseudo stop f3 p pseudo stop supply current (osc on) ?40 c 2 2. 85 c, 105 c, and 125 c refer to the "c", "v", and "m" temperature options, respectively. i dd ps reg 400 / 500 3 3. rti disabled / enabled. 600 / 700 3 a p25 c 2 400 / 500 3 600 / 700 3 a c85 c 2 800 / 1000 3 2000 / 2500 3 a c105 c 2 1200 / 1500 3 3500 / 4000 3 a p125 c 2 1500 / 2000 3 5500 / 6000 3 a f4 p stop supply current (t j = t a assumed) ?40 c 2 i dd s reg 30 150 a p2 5 c 2 30 150 a c8 5 c 2 330 2500 a c1 0 5 c 2 470 3500 a p1 2 5 c 2 660 5000 a table 16. mac71 x 1/6 1 device supply current characteristics ? 50 mhz notes: 1. mac71 x 2 characteristics are to be determined (tbd). conditions shown in ta b l e 7 , with f sys = 50 mhz. num c rating symbol typ max unit g1 p run supply current, single chip i dd r reg 120 150 ma g2 c doze supply current i dd d reg run doze pseudo stop g3 p pseudo stop supply current (osc on) ?40 c 2 2. 85 c, 105 c, and 125 c refer to the "c", "v", and "m" temperature options, respectively. i dd ps reg 400 / 500 3 3. rti disabled / enabled. 600 / 700 3 a p25 c 2 400 / 500 3 600 / 700 3 a c85 c 2 800 / 1000 3 2000 / 2500 3 a c105 c 2 1200 / 1500 3 3500 / 4000 3 a p125 c 2 1500 / 2000 3 5500 / 6000 3 a g4 p stop supply current (t j = t a assumed) ?40 c 2 i dd s reg 30 150 a p2 5 c 2 30 150 a c8 5 c 2 330 2500 a c1 0 5 c 2 470 3500 a p1 2 5 c 2 660 5000 a because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 13 3.7.4 voltage regulator characteristics table 17. vreg operating conditions num c characteristic symbol min typical max unit h1 p input voltages v vddra 3.15 ? 5.5 v h2 p output voltage, digital logic full performance mode reduced power mode shutdown mode v dd 2.5 2.45 1.60 ? 1 notes: 1. high impedance output. 2.5 2.5 ? 1 2.75 2.75 ? 1 v v v h3 p output voltage, pll full performance mode reduced power mode 2 reduced power mode 3 shutdown mode 2. current i dd pll = 1 ma (low power oscillator). 3. current i dd pll = 3 ma (standard oscillator). v dd pll 2.35 2.00 1.60 ? 1 2.5 2.5 2.5 ? 1 2.75 2.75 2.75 ? 1 v v v v h4 p low voltage interrupt 4 assert level negate level 4. monitors v dd a, active only in full performance mode. this interrupt indicates that i/o and atd performance may be degraded due to low supply voltage. v lv i a v lv i d 4.10 4.25 4.37 4.52 4.66 4.77 v v h5 p low voltage reset 5 assert level 5. monitors v dd 2.5, active only in full performance mode. only por is active in reduced performance mode. v lv r a 2.25 2.35 ? v h6 p power on reset 6 assert level negate level 6. monitors v dd 2.5, active in all modes. v pora v pord 0.97 ? ? ? ? 2.05 v v because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 14 3.7.5 chip power up and voltage drops the vreg sub-modules lvi (low volta ge interrupt), por (power on rese t) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. refer to figure 2 . figure 2. vreg chip power-up and voltage monitoring 3.7.6 output loads the on-chip voltage regulator is intended to supply the internal logic and oscillat or circuits. no external dc load is allowed. capacitive loads are specified in table 18 . capacitors with x7r dielectricum are required. table 18. vreg recommended load capacitances rating symbol min typ max unit load capacitance per v dd 2.5 pin 1 notes: 1. refer to table 38 for the specific number of v dd 2.5 pins on various packages. each v dd 2.5 pin should have the recommended loading as described in se ction 3.7.3, ?circuit board layout, ? of the mac7100 microcontroller family reference manual (mac7100rm). c lv d d 200 220 12000 nf load capacitance on v dd pll pin c lv d d f c p l l 90 220 5000 nf lv i d i s a bl e d due to lvr v lv i d v lvr d lv r por lv i v pord v lv r a v lv i a time lvi enabled v dd a v dd 2.5 v o l tage note: not to scale. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 15 3.8 clock and reset generator this section describes the electrical characteri stics for the oscillator, phase -locked loop, clock monitor and reset generator. 3.8.1 oscillator characteristics the mac7100 family features an internal low power loop controlled pierce oscillator and a full swing pierce oscillator/external clock mode. the selection of loop controll ed pierce oscillator or full swing pierce oscillator/exter nal clock depends on th e level of the xclks signal at the risi ng edge of the reset signal. before asserting the oscillator to the internal system clock distri bution subsystem, the quality of the oscillation is checked for each start from ei ther power on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or st op if a proper oscillation is not detected. the quality check also dete rmines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a cl ock monitor failure is a sserted if the frequenc y of the incoming clock signal is below the clock monitor assert frequency f cmfa . table 19. oscillator characteristics num c rating symbol min typ max unit j1a c crystal oscillator range (loop controlled pierce) f osc 1 notes: 1. if clksel[pllsel] is clear then the system clock ( f sys ) is equal to f osc , otherwise it is equal to f vco (table ta b l e 2 0 , k3 ). throughout this document, t sys is used to specify a unit of time equal to 1 f sys . 4.0 ? 16 mhz j1b c crystal oscillator range (full swing pierce) 2 3 2. depending on the crystal; a damping series resistor might be necessary 3. xclks asserted (low) during reset f osc 1 0.5 ? 40 mhz j2 p startup current i osc 100 ? ? a j3 c oscillator start-up time (loop controlled pierce) t uposc ?3 4 4. f osc = 4 mhz, c = 22 pf (refer to the mac7100 microcontroller family reference manual (mac7100rm) for circuit board layout recommendations, including oscillator capacitor placement and values). 50 5 5. maximum value is for extreme cases using high q, low frequency crystals ms j4 d clock quality check time-out t cqout 0.45 ? 2.5 s j5 p clock monitor failure assert frequency f cmfa 50 100 200 khz j6 p external square wave input frequency 3 f ext 0.5 ? 50 mhz j7 d external square wave pulse width low t extl 9.5 ? ? ns j8 d external square wave pulse width high t exth 9.5 ? ? ns j9 d external square wave rise time t extr ?? 1ns j10 d external square wave fall time t extf ?? 1ns j11 d input capacitance (extal, xtal pins) c in ?7?pf because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 16 3.8.2 pll filter characteristics the oscillator provides the referen ce clock for the pll as shown in figure 3 . the voltage controlled oscillator (vco) of the pll is also the system clock source in self clock mode. in order to operate reliably, care must be taken to select proper va lues for external loop filter components. figure 3. basic pll functional diagram the procedure described below can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table 20 . first, the vco gain at the desired vco output frequency is approximated by: eqn. 8 the phase detector relationship is given by: eqn. 9 i ch is the current in tracki ng mode. the loop bandwidth f c should be chosen to fulf ill the gardner?s stability criteria by at least a factor of 10, a typical value for the stability factor is 50. = 0.9 ensures a good transient response. eqn. 10 and finally the frequency re lationship is defined as: eqn. 11 with the above inputs the resi stance can be calculated as: eqn. 12 the capacitance c s can now be calculated as: eqn. 13 phase detector 1 refdv+1 k f ref v dd pll r c p c s k v loop divider 1 synr+1 f vco f osc 1 2 f cmp vco k v k 1 e f 1 f vco ? () k 1 1v ? ------------------------- - ? = k i ch ? k v ? = f c 2 f ref ?? 1 2 ++ () ? ---------------------------------------- 1 10 ------ f c f ref 410 ? -------------- 0.9 = () ;< < n f vco f ref ---------- 2 synr 1+ () ? == r 2 n f c ??? k --------------------------- - = c s 2 2 ? f c r ?? --------------------- 0.516 f c r ? ------------- 0.9 = () ; = because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 17 the capacitance c p should be chosen in the range of: eqn. 14 the stabilization delays shown in table 20 are dependant on pll operati onal settings and external component selection (for exampl e, the crystal and xfc filter). 3.8.2.1 jitter information with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly. the adju stment is done continuously with no abrupt changes in the clock output frequenc y. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the r eal minimum and maximu m clock periods as illustrated in figure 4. it is important to note that the pre-scal er used by timers and serial modules will eliminate the effect of p ll jitter to a large extent. figure 4. jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n ). thus, jitter is defined as: eqn. 15 for n < 100, the following equation is a good fit for the maximum jitter: eqn. 16 figure 5. maximum bus clock jitter approximation c s 20 c p c s 10 ? 0 t min1 123n ? 1n t nom t max1 t min (n) t max (n) jn () max 1 t max n () nt nom ? -------------------- ?1 t min n () nt nom ? -------------------- ?, ?? ?? = jn () j 1 n -------- j 2 += 01 5 10 20 15 n j(n) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 18 3.8.3 pll characteristics 3.8.4 crystal monitor time-out the time-out table 21 shows the delay for the crystal monitor to tr igger when the clock stops, either at the high or at the low level. the corresponding clock period with an ideal 50% duty cycle is twice this time-out value. 3.8.5 clock quality checker the timing for the clock quality check is derived fr om the oscillator and the vco frequency range in table 20 . these numbers define the upper time limit fo r the individual check windows to complete. table 20. pll characteristics num c rating symbol min typ max unit k1 pll reference frequency, crystal oscillator range f ref 0.5 ? 16 mhz k2 p self clock mode frequency f scm 2?5.5mhz k3 d vco locking range f vco 1 notes: 1. if clksel[pllsel] is set then the system clock ( f sys ) is equal to f vco , otherwise it is equal to f osc (table table 19 , j1a or j1b ). throughout this document, t sys is used to specify a unit of time equal to 1 f sys . 8?50mhz k4 d lock detector transition from acquisition to tracking mode | trk | 3?4% 2 2. percentage deviation from target frequency k5 d lock detection | lock | 0?1.5% 2 k6 d un-lock detection | unl | 0.5 ? 2.5 % 2 k7 d lock detector transition from tracking to acquisition mode | unt | 6?8% 2 k8 c pllon total stabilization delay (auto mode) 3 3. pll stabilization delay is highly dependent on operatio nal requirement and external component values (for example, crystal and xfc filt er component values). notes 4 and 5 show component values for a typical configurations. appropriate xfc filter values should be chosen based on operational requirement of system. t stab ?0.5 4 4. f osc = 4 mhz, f vco = 40 mhz (refdv = 0x00, synr = 0x04), c s = 2.2 nf, c p = 220 pf, r s = 5.6 k . 3 5 5. f osc = 4 mhz, f vco = 16 mhz (refdv = 0x00, synr = 0x01), c s = 4.7 nf, c p = 470 pf, r s = 2.7 k . ms k9 d pllon acquisition mode stabilization delay 3 t acq ?0.3 4 1 5 ms k10 d pllon tracking mode stabilization delay 3 t al ?0.2 4 2 5 ms k11 d charge pump current acquisition mode | i ch | ? 38.5 ? a k12 d charge pump current tracking mode | i ch | ?3.5? a k13 d jitter fit vco loop gain parameter k 1 ? ?195 ? mhz/v k14 d jitter fit vco loop frequency parameter f 1 ? 126 ? mhz k15 c jitter fit parameter 1 j 1 ??1.3% 4 k16 c jitter fit parameter 2 j 2 ? ? 0.12 % 4 table 21. crystal monitor time-outs min typ max unit 61 01 8 . 5 s table 22. crg maximum clock quality check timings clock check windows value unit check window 9.1 to 20.0 ms timeout window 0.46 to 1.0 s because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 19 3.8.6 startup table 23 summarizes several st artup characteristics. refer to section 4.3.6.10, ?crg operating mode details,? in the mac7100 microcontroller family reference manual (mac7100rm) for details. 3.8.6.1 power on and low voltage reset (por and lvr) the v porr and v pora levels are de rived from v dd 2.5. the v lvra level is derived from v dd 2.5. they are also valid if the device is powered externally. after releasing a por or lvr reset, the oscillator and clock quality checks start. after t cqout ( table 19 , j4 ) if no valid oscillation is detected, the mcu will start using the internal self-generated clock. the minimum startup time is given by t uposc ( table 19 , j3 ). 3.8.6.2 sram data retention sram content integrity is guaranteed if the crgflg[porf] bit is not set following a reset operation. 3.8.6.3 external reset when external reset is asserted for a time greater than pw rstl , the crg generates an internal reset and the cpu fetches the reset ve ctor without a clock qualit y check, if there was stable oscillation before reset. 3.8.6.4 stop recovery the mcu can return from stop to run mode in response to an external interrupt or an api. two delays occur before the mcu resumes execut ion. first, the voltage regulator must exit reduced power mode and return to full performance mode (t his assumes that the internal regulator is used rather than driving v dd 2.5 and v dd pll with an external regulator). second, a clock quality check is perfor med in the same manner as for a power-on reset before rele asing the clocks to the system. 3.8.6.5 pseudo stop recovery recovery from pseudo stop mode is similar to stop mode in that the vreg must return to fpm, but since the oscillator is not stoppe d there is no delay for clock stabilization. the mcu is returned to run mode by internal or external interrupts. 3.8.6.6 doze recovery recovery from doze mode avoids bot h the vreg and oscillator recovery periods. the mcu is returned to run mode by internal or external interrupts. table 23. crg startup characteristics num c rating symbol min typ max unit l1 d reset input pulse width pw rstl 2??t osc l2 d startup from reset n rst 192 ? 196 t osc l3 d xirq , irq pulse width, edge-sensitive mode pw irq 20 ? ? ns because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 20 3.9 external bus timing table 24 lists processor bus input timings, which are shown in figure 6 , figure 7 and figure 8 . note all processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. the reference clock is the clkout output. all other timing relationships can be derived from these values. figure 6. general input timing requirements table 24. external bus input timing specifications 1 notes: 1. assumes clkout is configured for full drive strength (via the pim config2_d[rds] bit). num c rating symbol min max unit m1 p clkout period 2 2. clkout is equal to the system clock, f sys . if clksel[pllsel] is set then f sys is equal to f vco (table table 20 , k3 ); if it is clear then f sys is equal to f osc (table table 19 , j1a or j1b ). throughout this document, t cyc is used to specify a unit of time equal to 1 clkout (which is equal to t fsys ). t cyc 20 ? ns control inputs m2a p control input valid to clkout high 3 3. the ta pin is the only control input on mac7100 family devices. t cvch 13 ? ns m3a p clkout high to control inputs invalid 3 t chcii 0?ns data inputs m4 p data input (data[15:0]) valid to clkout high t divch 9?ns m5 p clkout high to data input (data[15:0]) invalid t chdii 0?ns clkout (50 mhz) 1.5 v 1.5 v valid invalid invalid t setup t hold input setup & hold input rise time v h = v ih v l = v il t rise = 1.5 ns input fall time v h = v ih v l = v il t fall = 1.5 ns clkout inputs 1.5 v m4 m5 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 21 3.9.1 read and write bus cycles table 25 lists processor bus output timings. read/write bus timings listed in table 25 are shown in figure 7 and figure 8 . table 25. external bus output timing specifications 1 notes: 1. assumes clkout, cs n , bs n , oe , as , addr[21:0] and data[15:0] are configured for full drive strength (via the pim). num c rating symbol min max unit control outputs m6a p clkout high 2 to chip selects (cs [2:0]) valid 2. the cs n , bs n , oe and as signals are synchronous to the falling e dge of clkout. therefore, changes on these signals are triggered by the falling edge of clkout, even though they are specified in relation to the rising edge. t chcv ?0.5t cyc + 10 ns m6b p clkout high 2 to byte selects (bs [1:0]) valid t chbv ?0.5t cyc + 10 ns m6c p clkout high 2 to output select (oe ) valid t chov ?0.5t cyc + 10 ns m6d p clkout high 2 to address strobe (as ) valid t chasv ?0.5t cyc + 10 ns m7a p clkout high 2 to control output (bs [1:0], oe ) invalid t chcoi 0.5t cyc + 2 ? ns m7b p clkout high 2 to chip selects (cs [2:0]) invalid t chci 0.5t cyc + 2 ? ns m7c p clkout high 2 to address strobe (as ) invalid t chasi 0.5t cyc + 2 ? ns address and attribute outputs m8 p clkout high to address (addr[21:0]) and control (r/w) valid t chav ?1 0n s m9 p clkout high to address (addr[21:0]) and control (r/w ) invalid t chai 2?n s data outputs m10 p clkout high to data output (data[15:0]) valid t chdov ?1 3n s m11 p clkout high to data output (data[15:0]) invalid t chdoi 2?n s m12 d clkout high to data output (data[15:0]) high impedance t chdoz ?9n s because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 22 figure 7. read/write bus cycles, internal termination as (1) clkout cs n addr[21:0] oe r/w bs [1:0] s0 s2s1 s3 s4 s5 s0 s1 s2 s3 s4 s5 data[15:0] m6a m7b m6a m7b m8 m8 m8 m9 m6c m7a m1 m9 m6b m6b m7a m7a m4 m5 m10 m11 m12 m6d m7c m7c m6d 1. the ta / as signals are multiplexed on a single pin, so only one function may be used during bus transactions. ta (1) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 23 figure 8. read bus cycle, external termination ta (1) clkout cs n addr[21:0] oe r/w bs [1:0] s0 s2 s1 s3 s4 s5 s0 data[15:0] s1 m6a m7b m7a m7a m8 m9 m6c m6b m4 m5 m2a m3a 1. the ta / as signals are multiplexed on a single pin, so as is not available when external cycle termination is used. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 24 3.10 analog-to-digital converter table 26 and table 27 show conditions under which the atd operat es. the following constraints exist to obtain full-scale, full range results: v ss a v rl v in v rh v dd a. this constraint exists because the sample buffer amplifier cannot drive beyond the atd powe r supply levels. if the input level goes outside of this range it will effectively be clipped. table 26. atd operating characteristics in 5.0 v range conditions shown in ta b l e 7 unless otherwise noted num c rating symbol min typ max unit n1 d reference potential low high v rl v rh v ss a v dd a 2 ? ? v dd a 2 v dd a v v n2 c differential reference voltage 1 notes: 1. full accuracy is not guaranteed when differential voltage is less than 4.50 v v rh ? v rl 4.50 5.00 5.50 v n3 d atd clock frequency f at d c l k 0.5 ? 2.0 mhz n4 d atd 10-bit conversion period f at d c l k cycles 2 @ 2.0mhz f at d c l k 2. minimum time assumes a sample period of 2 atd clocks; maximum time assumes a sample period of 16 atd clocks. n conv10 t conv10 14 7 ? ? 28 14 cycles s n5 d atd 8-bit conversion period f at d c l k cycles 2 @ 2.0mhz f at d c l k n conv8 t conv8 12 6 ? ? 26 13 cycles s n6 d stop recovery time (v dd a = 5.0 v) t rec ??20 s n7 p reference supply current 1 atd module on i ref ? 0.200 0.255 ma n8 p reference supply current 2 atd modules on i ref ? 0.400 0.510 ma table 27. atd operating characteristics in 3.3 v range conditions shown in ta b l e 7 , with v dd x = 3.3 v ?5/+10% and a temperature maximum of +140 c unless otherwise noted. num c rating symbol min typ max unit p1 d reference potential low high v rl v rh v ss a v dd a 2 ? ? v dd a 2 v dd a v v p2 c differential reference voltage 1 notes: 1. full accuracy is not guaranteed when differential voltage is less than 3.15 v v rh ? v rl 3.15 3.3 3.6 v p3 d atd clock frequency f at d c l k 0.5 ? 2.0 mhz p4 d atd 10-bit conversion period f at d c l k cycles 2 @ 2.0mhz f at d c l k 2. minimum time assumes a sample period of 2 atd clocks; maximum time assumes a sample period of 16 atd clocks. n conv10 t conv10 14 7 ? ? 28 14 cycles s p5 d atd 8-bit conversion period f at d c l k cycles 2 @ 2.0mhz f at d c l k n conv8 t conv8 12 6 ? ? 26 13 cycles s p6 d stop recovery time (v dd a = 3.3 v) t rec ??20 s p7 p reference supply current 1 atd module on i ref ? 0.130 0.170 ma p8 p reference supply current 2 atd modules on i ref ? 0.260 0.340 ma because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 25 3.10.1 factors influencing accuracy three factors?source resi stance, source capacitance and current injection?have an influence on the accuracy of the atd. 3.10.1.1 source resistance due to the input pin leakage current as specified in table 8 in conjunction with the source resistance there will be a voltage drop fr om the signal source to the atd input. th e maximum specified source resistance r s , results in an error of less than 1/2 lsb (2.5 mv ) at the maximum leakage current. if the device or operating conditions are less than the worst case, or l eakage-induced errors are acceptable, larger values of source resistance are allowed. 3.10.1.2 source capacitance when sampling, an additional internal capacitor is switched to the input . this can cause a voltage drop due to charge sharing with the external capacitance and the pin capacitance. for a maximum sampling error of the input voltage 1 lsb, then the external filter capacitor must be calculated as, c f 1024 (c ins ? c inn ) . 3.10.1.3 current injection there are two cases to consider: 1. a current is injected into the channel being converted. the channel bei ng stressed has conversion values of 0x3ff (0xff in 8-bit mode) for analog inputs greater than v rh and 0x000 for values less than v rl unless the current is higher than specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ra tio k), this additional current impacts the accuracy of the conversion depe nding on the source resistance. th e additional input voltage error on the converted channel can be calculated as v err = k r s i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table 28. atd electrical characteristics conditions are shown in ta bl e 7 unless otherwise noted num c rating symbol min typ max unit q1 c max input source resistance r s ?? 1k q2 c total input capacitance non sampling sampling c inn c ins ? ? 10 22 ? ? pf pf q3 c disruptive analog input current i na ?2.5 ? 2.5 ma q4 c coupling ratio positive current injection k p ??tbda / a q5 c coupling ratio negative current injection k n ??tbda / a because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 26 3.10.2 atd accuracy table 29 and table 30 specify the atd conversi on performance excluding any errors due to current injection, input capacitan ce and source resistance. for the following definitions, see figure 9 . differential non-linearity (dnl) is defined as the differ ence between two adjacent switching steps: eqn. 17 the integral non-linearity (inl) is defined as the sum of all dnls: eqn. 18 table 29. atd conversion performance in 5.0 v range conditions shown in ta b l e 7 except as noted here: f at d c l k = 2.0 mhz, 4.5 v v dd a 5.5 v num c rating symbol min typ max unit r1 p 10-bit resolution lsb ? 5 1 notes: 1. assumes v ref = v rh ? v rl = 5.12 v, other v ref conditions result in different lsb resolutions. ?mv r2 p 10-bit differential nonlinearity dnl ?1 ? 1 counts r3 p 10-bit integral nonlinearity inl ?2.5 1.5 2.5 counts r4 p 10-bit absolute error 2 2. these values include the quantization error which is inherently ? count for any a/d converter. ae ?3 2.0 3 counts r5 p 8-bit resolution lsb ? 20 1 ?mv r6 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts r7 p 8-bit integral nonlinearity inl ?1.0 0.5 1.0 counts r8 p 8-bit absolute error 2 ae ?1.5 1.0 1.5 counts table 30. atd conversion performance in 3.3 v range conditions shown in ta b l e 7 except as noted here: f at d c l k = 2.0 mhz, 3.15 v v dd a 3.6 v num c rating symbol min typ max unit s1 p 10-bit resolution lsb ? 3.25 1 notes: 1. assumes v ref = v rh ? v rl = 3.33 v, other v ref conditions result in different lsb resolutions. ?mv s2 p 10-bit differential nonlinearity dnl ?1.5 ? 1.5 counts s3 p 10-bit integral nonlinearity inl ?3.5 1.5 3.5 counts s4 p 10-bit absolute error 2 2. these values include the quantization error which is inherently ? count for any a/d converter. ae ?5 2.0 5 counts s5 p 8-bit resolution lsb ? 13 1 ?mv s6 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts s7 p 8-bit integral nonlinearity inl ?1.5 1.0 1.5 counts s8 p 8-bit absolute error 2 ae ?1.5 1.0 1.5 counts dnl i () v i v i1 ? ? 1 lsb ---------------------- 1 ? = inl n () dnl i () i1 = n v n v 0 ? 1 lsb ------------------ - n ? == because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 27 figure 9. atd accuracy definitions note figure 9 shows only definitions, for sp ecification values refer to table 29 . 0x3ff 0x3fe 0x3fd 0x3fc 0x3fb 0x3fa 0x3f9 0x3f8 0x3f7 0x3f6 0x3f5 0x3f4 0x3f3 9 8 7 6 5 4 3 2 1 0 0 10203040505055 5065 5075 5085 5095 5105 5115 5060 5070 5080 5090 5100 5110 5120 5 152535 1 2 0xfd 0xfe 0xff 10-bit absolute error boundary ideal transfer curve 8-bit transfer curve 10-bit transfer curve 8-bit absolute error boundary 10-bit resolution 8-bit resolution lsb dnl v i?1 vi v in mv because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 28 3.10.3 atd timing specifications figure 10. atd external trigger timing diagram table 31. atd external trigger timing specifications num c parameter symbol min max unit t1 d etrig period (level-sensitive trigger mode) t period 1 + n conv n 1 notes: 1. n conv n denotes 8- or 10-bit conversion time (refer to specifications n4 , n5 , p4 and p5 ). in order to achieve the minimum period between conversions when using level-sensit ive triggering, etrig must remain asserted this long. ? f atdclk cycles t2 d etrig minimum pulse width edge-sensitive trigger mode level-sensitive trigger mode t pw 1 2 ? ? f atdclk cycles t3 d etrig level recovery 2 2. time prior to the end of a conversion that etrig must be negated in order to prevent the start of another conversion. t lr 1? f atdclk cycles t4 d conversion start delay t dly ?2 f atdclk cycles level sensitive low active sequence conversion activity complete flag low active sequence complete flag conversion activity level sensitive falling edge active conversion activity edge sensitive etrig an n _ x etrig ascif an n _ x etrig ascif an n _ x t2 t1 t4 t4 t2 t4 t4 t4 t3 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 29 3.11 serial peripheral interface 3.11.1 master mode master mode timing values are shown in table 32 and illustrated in figure 11 and figure 12 . 3.11.2 slave mode slave mode timing values are shown in table 33 and illustrated in figure 13 and figure 14. table 32. spi master mode timing characteristics conditions are shown in ta bl e 7 unless otherwise noted, c load = 200 pf on all outputs num c rating symbol min typ max unit u1a p operating frequency (baud rate) f op 1 notes: 1. refer to mac7100 microcontroller family reference manual (mac7100rm) chapter 22 for all available baud rates. ?? 2 2. on mask set l49p and l47w devices, u1a maximum = ? and u1b minimum = 4. f ips u1b p sck period (t sck = 1 f op , t ips = 1 f ips )t sck 1 2 2 ?7 32,768 t ips u2 d enable lead time t lead ???t sck u3 d enable lag time t lag ???t sck u4 d clock (sck) high or low time t wsck t ips ? 30 ? 1024 t ips ns u5 d data setup time (inputs) t su 25 ? ? ns u6 d data hold time (inputs) t hi 0??ns u9 d data valid (after enable edge) t v ??25ns u10 d data hold time (outputs) t ho 0??ns u11 d rise time inputs and outputs t r ??25ns u12 d fall time inputs and outputs t f ??25ns table 33. spi slave mode timing characteristics conditions are shown in ta bl e 7 unless otherwise noted, c load = 200 pf on all outputs num c rating symbol min typ max unit v1a p operating frequency f op ?? 1 notes: 1. on mask set l49p and l47w devices, v1a maximum = ? and v1b minimum = 4. f ips v1b p sck period (t sck = 1 f op , t ips = 1 f ips )t sck 2 1 ?7 32,768 t ips v2 d enable lead time t lead 1??t ips v3 d enable lag time t lag 1??t ips v4 d clock (sck) high or low time t wsck t ips ? 30 ? ? ns v5 d data setup time (inputs) t su 25 ? ? ns v6 d data hold time (inputs) t hi 25 ? ? ns v7 d slave access time t a ?? 1t ips v8 d slave sin disable time t dis ?? 1t ips v9 d data valid (after sck edge) t v ??25ns v10 d data hold time (outputs) t ho 0??ns v11 d rise time inputs and outputs t r ??25ns v12 d fall time inputs and outputs t f ??25ns 1 732678 , ---------------------------- - 1 732678 , ---------------------------- - because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 30 figure 11. spi master timing (cpha = 0) figure 12. spi master timing (cpha = 1) msb out (2) msb in (2) pcs x sck (cpol = 0) (output) sck (cpol = 1) (output) (output) bit 6 ... 1 sin (input) sout (output) lsb out lsb in bit 6 ... 1 u2 u1b u3 u4 u4 u12 u5 u6 u11 u9 u9 u10 1. if configured as output. 2. lsbfe = 0. for lsbfe = 1, bit order is lsb, bit 1, ..., bit 6, msb. pcs x sck (cpol = 0) (output) sck (cpol = 1) (output) (output) bit 6 ... 1 sin (input) sout (output) lsb in bit 6 ... 1 port data port data master lsb out u10 u9 u6 u11 u12 u11 u5 u4 u4 u2 u1b u3 u12 msb out (2) msb in (2) 1. if configured as output. 2. lsbfe = 0. for lsbfe = 1, bit order is lsb, bit 1, ..., bit 6, msb. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 31 figure 13. spi slave timing (cpha = 0) figure 14. spi slave timing (cpha = 1) ss sck (cpol = 0) (input) sck (cpol = 1) (input) (input) sout (output) sin (input) slave msb out bit 6 ... 1 slave lsb out msb in lsb in bit 6 ... 1 v2 v1b v4 v4 v5 v6 v7 v8 v9 v10 v10 v12 v12 v11 v11 v3 ss sck (cpol = 0) (input) sck (cpol = 1) (input) (input) bit 6 ... 1 sout (output) sin (input) slave msb out slave lsb out msb in lsb in bit 6 ... 1 v2 v1b v4 v4 v5 v6 v7 v8 v9 v10 v12 v12 v11 v11 v3 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 32 3.12 flexcan interface 3.13 common flash module note unless otherwise noted the abbrevia tion nvm (non-volatile memory) is used for both program flash and data flash. the time base for all program and data flash operations, f nvmop , is derived from the ips bus clock, f ips , using the cfmclkd register to control th e divider ratio. throughout this section, t ips refers to 1 f ips , and t nvmop refers to 1 f nvmop . an f nvmop frequency range li mit is imposed for performing program or erase operations. the cfm does not monitor the frequency and will not prevent program or erase operation at frequencies above or below the following limits: eqn. 19 f nvmop = 200 khz gives the fastest progr am and erase performance. se tting cfmclkd to a value such that f nvmop < 150 khz should be avoided, as th is can damage the flash memory due to overstress. setting cfmclkd to a value such that f nvmop > 200 khz can result in incomplete programming or erasure of the flash memory array cells. 3.13.1 mass erase timing the time required to erase the entire nvm array (both program and data) is calculated using the formula: eqn. 20 the setup time can be ignored for this operation. 3.13.2 blank check timing the time it takes to perform a blank check on the program or data flash is dependant on the location of the first non-blank word, starting from relative address zero. one f ips cycle is required per word to be verified, and the time required for the operatio n is calculated using the formula: eqn. 21 table 34. flexcan wake-up pulse characteristics conditions are shown in ta bl e 7 unless otherwise noted num c rating symbol min typ max unit w1 p flexcan wake-up dominant pulse filtered t wup ?? 2 s w2 p flexcan wake-up dominant pulse passed t wup 5?? s 150 khz f nvmop 200 khz < t mass 20000 t nvmop ? t check locations 15 + () t ips ? = because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 33 3.13.3 page erase timing the time required to erase a 4 kbyte program or 1 kbyte data flash logical page is calculated using the formulas: eqn. 22 eqn. 23 3.13.4 page erase verify timing the time required to verify that a program flash pa ge is erased depends on the location of the first non-blank word. the time requi red for the operation is calculated using the formula: eqn. 24 the time required to verify that a data flash page is erased is calculated using the formula: eqn. 25 3.13.5 programming timing programming time is dependant on the f ips and f nvmop frequencies, and is calculated for a single word using the formula: eqn. 26 burst programming can be utilized with the program flash, wh ere up to 32 words in a row can be programmed consecutively by keeping the command pipe line filled. the time to program a consecutive word is calculated using the formula: eqn. 27 therefore, the time to program a 32-wo rd row is calculated using the formula: eqn. 28 note that burst programming is more than 2 times faster than single word programming. 3.13.6 data signature timing 1 the time required to perform a data signature command is dependant on the number of words or half-words compressed during the operati on, and is calculated using the formula: eqn. 29 1. this feature is not available on mask set l49p and l47w devices. t erap 4096 t nvmop ? 15 + t ips ? = t erad 1024 t nvmop ? 15 + t ips ? = t pevp 4 1024 4 ---------------------- ?? ?? 15 + t ips = t pevd 1 1024 4 ---------------------- ?? ?? 15 + t ips = t swpgm 9t nvmop ? 25 t ips ? + = t bwpgm 4t nvmop ? 9t ips ? + = t brpgm t swpgm 31 t bwpgm ? += t dsig words or half-words 15 + () t ips ? = because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary electrical characteristics freescale semiconductor 34 3.13.7 cfm timing specifications table 35 lists the time required to execute various operations described in the section 3.13.1 through section 3.13.6. for operating conditions other than those assumed below, equation 19 through equation 29 must be used to calculate the timing for specific commands under those conditions. table 35. cfm timing characteristics conditions are shown in ta bl e 7 unless otherwise noted num c rating symbol min typ max unit x1 d system clock f nvm f sys 0.5 ? 50 1 notes: 1. subject to restrictions in table 19 and table 20 for operating characteristics of the oscillator and pll. mhz x2 d bus frequency for programming or erase operations f nvm f ips 1??mhz x3 d program/erase operating frequency f nvmop 150 ? 200 khz x4 p programming time, 2 single word 2. minimum erase and programming times are achieved with the indicated maximum f sys (which is f ips 2, and subject to the limits of table 19 and ta b l e 2 0 ) and corresponding maximum f nvmop . maximum erase and programming times are dependent on the combination of f nvmop and f ips ; values shown are calculated for f ips = 2 mhz and f nvmop = 154 khz . f sys = 50 mhz t swpgm 47.1 ? 71.0 s f sys = 40 mhz 48.1 ? 71.0 x5 d programming time, 2 consecutive word burst f sys = 50 mhz t bwpgm 20.8 ? 30.5 s f sys = 40 mhz 21.3 ? 30.5 x6 d programming time, 2 32-word row burst f sys = 50 mhz t brpgm 693.1 ? 1,016.5 s f sys = 40 mhz 706.8 ? 1,016.5 x7a p page erase time, 2 program flash f sys = 50 mhz t erap 21.0 ? 26.6 ms f sys = 40 mhz 21.3 ? 26.6 x7b p page erase time, 2 data flash f sys = 50 mhz t erad 5.2 ? 6.7 ms f sys = 40 mhz 5.3 ? 6.7 x8 p mass erase time 2 t mass 100 ? 130 ms x9a d blank check time, 3 program flash per block 3. minimum blank check or page erase verify time assumes the first word in the array is blank and the second is not. maximum blank check or page erase verify time assumes the entire block or page is blank. mac71 x 1, mac71 x6t bcheckp 16 ? 131,087 t ips mac71 x21 6?6 5 , 5 5 1 x9b d blank check time, 3 data flash per block t bcheckd 16 ? 8,207 t ips x9c d page erase verify time 3 program flash t pevp 16 ? 1,039 t ips data flash t pevd 16 ? 271 x10 d data signature time 4 4. data signature timing is dependant on the number of words or half-words compressed for the program and data arrays, respectively. minimum time is for two words or half-words; maximum time is for the entire array. mac71 x 6, program t dsig 17 ? 262,159 t ips mac71 x 1, program 17 ? 131,087 mac71 x 2, program 17 ? 65,551 mac71 xx , data 17 ? 16,399 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
electrical char acteristics mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 35 3.13.8 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at the opera ting conditions noted. the program/era se cycle count on the sector is incremented every time a sector or mass erase event is executed. note all values shown in table 36 are target values and subject to characterization. for flash cycling pe rformance, each program operation must be preceded by an erase. table 36. nvm reliability characteristics conditions shown in ta b l e 7 unless otherwise noted. num c rating min unit x11 c program/data flash program/eras e endurance (?40c to +125c) 10,000 cycles x12 c program/data flash data retention lifetime 15 years because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 36 4 device pin assignments the mac7100 family is available in 208-pin ball gr id array (map bga), 144-pin low profile quad flat (lqfp), 112-pin lqfp, and 100-pin lqfp package opti ons. the family of device s offer pin-compatible packaged devices to assi st with system development and accommoda te a direct application enhancement path. refer to table 2 for a comparison of the peripheral sets and package options for each device. most pins perform two or more functions, wh ich are described in more detail in the mac7100 microcontroller family reference manual (mac7100rm). table 37 , table 38 and figure 15 through figure 22 show the pin assignments for various devices and packages. table 37. signal pin assignments primary / gpio function peripheral function 1 external bus function 1 debug function 1 read on reset pin number (by device) 7101 7106 7111 7116 7112 7121 7126 7122 7131 7136 7141 7142 extal ? ? ? ? 60 60 60 48 48 t10 t10 45 xtal ? ? ? ? 61 61 61 49 49 t11 t11 46 xfc ? ? ? ? 58 58 58 46 46 t9 t9 43 reset ? ? ? ? 48 48 48 36 36 t7 t7 33 tdi ? ? ? ? 128 128 128 102 102 a8 a8 93 tdo ? ? ? ? 129 129 129 103 103 b8 b8 94 tck ? ? ? ? 130 130 130 104 104 a7 a7 95 tms ? ? ? ? 131 131 131 105 105 b7 b7 96 ??t a / as 2 ? ? ? 79???m14m14? pa 0 ? data 0 3 mcko 4 ? 138 138 138 106 106 b5 b5 ? pa 1 ? data 1 3 evto ? 137 137 137 ? ? c5 c5 ? pa 2 ? data 2 3 evti ? 136 136 136 ? ? a5 a5 ? pa 3 ? data 3 3 mdo0 ? 135 135 135 ? ? c6 c6 ? pa 4 ? data 4 3 mdo1 ? 134 134 134 ? ? b6 b6 ? pa 5 ? data 5 3 mseo ? 133 133 133 ? ? a6 a6 ? pa 6 ? data 6 3 rdy ? 132 132 132 ? ? c7 c7 ? pa 7 ? data 7 3 ? ? ? 98987474h15h15 65 pa 8 ? data 8 3 ? ? ? 97977373h13h13 64 pa 9 ? data 9 3 ? ? ? 96967272h14h14 63 pa 1 0 ? data 1 0 3 ? ? ? 95957171h16h16? pa 1 1 ? data 1 1 3 ? ? ? 94947070j15j15? pa 1 2 ? data 1 2 3 ? ? ? 93936969j14j14? pa 1 3 ? data 1 3 3 ? ? 67 67 67 53 53 r12 r12 ? pa 1 4 ? data 1 4 3 ?ps 3 66 66 66 52 52 t12 t12 ? pa 1 5 ? data 1 5 3 ?aa 3 65 65 65 51 51 p11 p11 48 pb0 sda ? ? ? 15 15 15 11 11 g1 g1 8 pb1 scl ? ? ? 16 16 16 12 12 h3 h3 9 pb2 sin_a ? ? ? 17 17 17 13 13 h2 h2 10 pb3 sout_a ? ? ? 18 18 18 14 14 h1 h1 11 pb4 sck_a ? ? ? 19 19 19 15 15 j3 j3 12 pb5 pcs0_a / ss_a ? ? ? 20 20 20 16 16 j1 j1 13 pb6 pcs1_a ? ? ? 21 21 21 17 17 j2 j2 14 pb7 pcs2_a ? ? ? 22 22 22 18 18 k1 k1 15 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 37 pb8 pcs5_a / pcss_a ? ? ? 23 23 23 19 19 k2 k2 16 pb9 pcs0_b / ss_b ? ? ? 72 72 72 56 56 t14 t14 51 pb10 pcs5_b / pcss_b ? ? ? 73 73 73 57 5 57 r14 r14 52 pb11 pcs2_b ? ? ? 74 74 74 ? 5 ?n14n14 53 pb12 pcs1_b ? ? ? 75 75 75 58 58 p15 p15 54 pb13 sck_b ? ? ? 76 76 76 59 59 p16 p16 55 pb14 sout_b ? ? ? 77 77 77 60 60 n15 n15 56 pb15 sin_b ? ? ? 78 78 78 61 61 n16 n16 57 pc0 ? addr0 3 ? ? 999??f1f1? pc1 ? addr1 3 ? ? 10 10 10 ? ? f3 f3 ? pc2 ? addr2 3 ? ? 11 11 11 ? ? g2 g2 ? pc3 ? addr3 3 ? ? 12 12 12 ? ? g3 g3 ? pc4 ? addr4 3 ? ? 28 28 28 ? ? l3 l3 ? pc5 ? addr5 3 ? ? 29 29 29 ? ? m2 m2 ? pc6 ? addr6 3 ? ? 30 30 30 ? ? m3 m3 ? pc7 ? addr7 3 ? ? 31 31 31 ? ? n3 n3 ? pc8 ? addr8 3 ? ? 44 44 44 ? ? p5 p5 ? pc9 ? addr9 3 ? ? 45 45 45 ? ? r6 r6 ? pc10 ? addr10 3 ? ? 46 46 46 ? ? p6 p6 ? pc11 ? addr11 3 ? ? 47 47 47 ? ? t6 t6 ? pc12 ? addr12 3 ???8888??k14k14? pc13 ? addr13 3 ???8989??k13k13? pc14 ? addr14 3 ???9090??k15k15? pc15 ? addr15 3 ? ? ?91916767j16j16? pd0 ? bs0 3 ? modb 7070705454t13t13 49 pd1 ? bs1 3 ? moda 7171715555r13r13 50 pd2 6 ?clkout? xclks 80 80 80 62 62 m16 m16 58 pd3 xirq ? ? ? 81 81 81 63 63 m15 m15 59 pd4 irq ? ? ? 82 82 82 64 64 l16 l16 60 pd5 ? addr16 3 ? ? ? 92926868j13j13? pd6 ? addr17 3 ? ? ? 119 119 95 95 c10 c10 86 pd7 ? addr18 3 ? ? ? 120 120 96 96 d10 d10 87 pd8 ? addr19 3 ? ? ? 121 121 97 97 d9 d9 88 pd9 ? addr20 3 ? ? ? 122 122 98 98 b9 b9 89 pd10 ? addr21 3 ? ? ? 123 123 99 99 d8 d8 90 pd11 ? oe 3 ? ? 68 68 68 ? ? p12 p12 ? pd12 ? cs2 3 ? ? 69 69 69 ? ? p13 p13 ? pd13 ? cs1 3 ? ? 83 83 83 ? ? l13 l13 ? pd14 ? cs0 3 ? ? 84 84 84 ? ? l14 l14 ? pd15 ? r/w 3 ? ? 85 85 85 ? ? l15 l15 ? pe0 an0_a ? mcko' ? 89 99 99 75 75 g16 g16 66 pe1 an1_a ? evto ' ? 91 100 100 76 76 g15 g15 67 table 37. signal pin assignments (continued) primary / gpio function peripheral function 1 external bus function 1 debug function 1 read on reset pin number (by device) 7101 7106 7111 7116 7112 7121 7126 7122 7131 7136 7141 7142 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 38 pe2 an2_a ? evti ' ? 93 101 101 77 77 f13 f13 68 pe3 an3_a ? mdo0' ? 95 102 102 78 78 f14 f14 69 pe4 an4_a ? mdo1' ? 97 103 103 79 79 e13 e13 70 pe5 an5_a ? mseo ' ? 99 104 104 80 80 e14 e14 71 pe6 an6_a ? rdy ' ? 101 105 105 81 81 d15 d15 72 pe7 an7_a ? ? ? 103 106 106 82 82 c15 c15 73 pe8 an8_a ? ? ? 105 107 107 83 83 c14 c14 74 pe9 an9_a ? ? ? 107 108 108 84 84 d14 d14 75 pe10 an10_a ? ? ? 113 113 113 89 89 b13 b13 80 pe11 an11_a ? ? ? 115 114 114 90 90 c12 c12 81 pe12 an12_a ? ? ? 117 115 115 91 91 a12 a12 82 pe13 an13_a ? ? ? 119 116 116 92 92 b11 b11 83 pe14 an14_a ? ? ? 121 117 117 93 93 a10 a10 84 pe15 an15_a ? ? ? 123 118 118 94 94 a9 a9 85 pf0 emios0 ? debug status 7 nexps 43 43 43 35 35 t5 t5 32 pf1 emios1 ? debug status 7 nexpr 42 42 42 34 34 r5 r5 31 pf2 emios2 ? debug status 7 ? 4141413333t4t4 30 pf3 emios3 ? debug status 7 ? 4040403232r4r4 29 pf4 emios4 ? debug status 7 ? 3939393131t3t3 28 pf5 emios5 ? debug status 7 ? 3838383030p4p4 27 pf6 emios6 ? debug status 7 ? 3737372929r3r3 26 pf7 emios7 ? debug status 7 ? 3636362828r1r1 25 pf8 emios8 ? debug status 7 ? 3535352727p2p2 24 pf9 emios9 ? debug status 7 ? 3434342626p1p1 23 pf10 emios10 ? debug status 7 ? 3333332525n2n2 22 pf11 emios11 ? debug status 7 ? 3232322424n1n1 21 pf12 emios12 ? debug status 7 ? 2727272323m1m1 20 pf13 emios13 ? debug status 7 ? 2626262222l2l2 19 pf14 emios14 ? debug status 7 ? 2525252121l1l1 18 pf15 emios15 ? debug status 7 ? 2424242020k3k3 17 pg0 rxd_b ? ? ? 141 141 141 109 109 a3 a3 97 pg1 txd_b ? ? ? 142 142 142 110 110 c4 c4 98 pg2 rxd_a ? ? ? 143 143 143 111 111 b3 b3 99 pg3 txd_a ? ? ? 144 144 144 112 112 c2 c2 100 pg4 cntx_a ? ? ? 1 1 1 1 1 d3 d3 1 pg5 cnrx_a ? ? ? 22222c1c1 2 pg6 cntx_b ? ? ? 7 7 7 7 7 e1 e1 3 pg7 cnrx_b ? ? ? 88888f2f2 4 pg8 cntx_c 8 ? ? ? 33333d2d2? pg9 cnrx_c 8 ? ? ? 44444d1d1? pg10 cntx_d 8 ? ? ? 55555e3e3? pg11 cnrx_d 8 ? ? ? 66666e2e2? pg12 rxd_d 8 ? ? ? 51 51 51 39 39 r7 r7 36 pg13 txd_d 8 ? ? ? 52 52 52 40 40 r8 r8 37 table 37. signal pin assignments (continued) primary / gpio function peripheral function 1 external bus function 1 debug function 1 read on reset pin number (by device) 7101 7106 7111 7116 7112 7121 7126 7122 7131 7136 7141 7142 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 39 pg14 rxd_c ? ? ? 139 139 139 107 107 a4 a4 ? pg15 txd_c ? ? ? 140 140 140 108 108 b4 b4 ? ph0 an0_b ? ? ? 88 ? ? ? ? g13 g13 ? ph1 an1_b ? ? ? 90 ? ? ? ? g14 g14 ? ph2 an2_b ? ? ? 92 ? ? ? ? f16 f16 ? ph3 an3_b ? ? ? 94 ? ? ? ? f15 f15 ? ph4 an4_b ? ? ? 96 ? ? ? ? e16 e16 ? ph5 an5_b ? ? ? 98 ? ? ? ? e15 e15 ? ph6 an6_b ? ? ? 100 ? ? ? ? d16 d16 ? ph7 an7_b ? ? ? 102 ? ? ? ? c16 c16 ? ph8 an8_b ? ? ? 104 ? ? ? ? b16 b16 ? ph9 an9_b ? ? ? 106 ? ? ? ? b14 b14 ? ph10 an10_b ? ? ? 108 ? ? ? ? d13 d13 ? ph11 an11_b ? ? ? 114 ? ? ? ? a13 a13 ? ph12 an12_b ? ? ? 116 ? ? ? ? b12 b12 ? ph13 an13_b ? ? ? 118 ? ? ? ? c11 c11 ? ph14 an14_b ? ? ? 120 ? ? ? ? a11 a11 ? ph15 an15_b ? ? ? 122 ? ? ? ? b10 b10 ? pi0 pcs3_a ? ? ? ??????c3? pi1 pcs4_a ? ? ? ??????d5? pi2 pcs6_a ? ? ? ??????d4? pi3 pcs7_a ? ? ? ??????e4? pi4 pcs3_b ? ? ? ??????g4? pi5 pcs4_b ? ? ? ??????j4? pi6 pcs6_b ? ? ? ??????k4? pi7 pcs7_b ? ? ? ??????l4? pi8 ? ? ? ? ??????n4? pi9 ? ? ? ? ??????p3? pi10 ? ? ? ? ??????r2? pi11 ? ? ? ? ??????r15? pi12 ? ? ? ? ??????n11? pi13 ? ? ? ? ??????n12? pi14 ? ? ? ? ??????n13? pi15 ? ? ? ? ??????p14? notes: 1. the mac7100 family maximum peripheral configurations are listed in these columns. some family members do not implement the f ull complement of atd, can, dspi and esci peripherals. refer to table 2 on page 3 for availability of peripheral functions on various devices. 2. as function not available on mask set l49p devices. 3. mac7111, mac7116, mac7131 and mac7136 only. 4. the mcko function cannot be used on mac7121 devices (the alternate nexus port must be used). 5. on mac7121 mask set l49p devices, pb11 / pcs2_b is bonded out on pin 57. 6. pd2 function not available on mask set l49p devices. 7. optional debug status port not available on mask set l49p devices. 8. can c, can d and esci d not available on mac7112, mac7122 and mac7142 devices. table 37. signal pin assignments (continued) primary / gpio function peripheral function 1 external bus function 1 debug function 1 read on reset pin number (by device) 7101 7106 7111 7116 7112 7121 7126 7122 7131 7136 7141 7142 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 40 table 38. power supply, voltage regulator and reference pin assignments pin name pin number (by device) 7101 / 7106 / 7111 / 7112 / 7116 7121 / 7122 / 7126 7131 / 7136 7141 / 7142 v dd x 14, 50, 64, 87, 124 10, 38, 66 c9, h4, k16, p7, p10 6, 35, 62 v ss x 13, 49, 63, 86, 125 7101 / 7106 / 7112 only: 79 9, 37, 65 a1, a2, b1, b2, f4, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, m4, m13, r9, r10, r16, t1, t2, t15, t16 7131 only: c3, d4, d5, e4, g4, j4, k4, l4, n4, n11, n12, n13, p3, p14, r9, r10 5, 34, 61 v dd r5 6 4 4 p 9 4 1 v ss r 55 43 n5, n6 40 v dd 2.5 53, 127 41, 101 c8, p8 38, 92 v ss 2.5 54, 126 42, 100 d6, d7, n7, n8 39, 91 v dd pll 57 45 t8 42 v ss pll 59 47 n9, n10 44 v dd a 109 85 a16, b15, c13 76 v ss a 112 88 d11, d12 79 v rh 110 86 a15 77 v rl 111 87 a14 78 test 1 notes: 1. this pin is reserved for freescale factory testing, and must be tied to system groun d in all applications. 62 50 r11 47 n/c??? 7 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 41 4.1 mac7141 pin diagram figure 15. pin assignments for mac7141 in 100-pin lqfp pg4 pg5 pg6 pg7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 pf7 pb11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 mac7141 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7 pa8 pa9 v dd x v ss x pd4 pd3 pb15 pb14 pb13 pb10 pb9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pg3 pg2 pg1 pg0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a vrl vrh v dd a 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa15 pd0 pd1 pb12 / / / / / / / / / / / / / / / / / / / / / / ss_a pcss_a v ss x v dd x n/c / / cntx_a cnrx_a cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 / / / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda nexpr nexps / / / pcs2_b / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / irq / xirq / clkout / sin_b / sout_b / sck_b / pcs5_b / pcs0_b / pcs1_b / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b / ss_b / txd_a / rxd_a / txd_b / rxd_b / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a 1. pd2 function not available on l49p mask set devices. pd2 (1) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 42 4.2 mac7142 pin diagram figure 16. pin assignments for mac7142 in 100-pin lqfp pg4 pg5 pg6 pg7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 pf7 pb11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 mac7142 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7 pa8 pa9 v dd x v ss x pd4 pd3 pd2 pb15 pb14 pb13 pb10 pb9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pg3 pg2 pg1 pg0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a vrl vrh v dd a 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa15 pd0 pd1 pb12 / / / / / / / / / / / / / / / / / / / / / / ss_a pcss_a v ss x v dd x n/c / / cntx_a cnrx_a cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 modb moda nexpr nexps / / / pcs2_b / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / irq / xirq / clkout / sin_b / sout_b / sck_b / pcs5_b / pcs0_b / pcs1_b / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b / ss_b / txd_a / rxd_a / txd_b / rxd_b / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 43 4.3 mac7121 / mac7126 pin diagram figure 17. pin assignments for mac7121 / mac7126 in 112-pin lqfp mac7121 / mac7126 (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 112 lqfp 28 pf7 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa 7 pa 8 pa 9 pa 1 0 pa 1 1 pa 1 2 pd5 pc15 v dd x v ss x pd4 pd3 pb15 pb14 pb13 pb12 57 pb10 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 pg3 pg2 pg1 pg0 pg15 pg14 pa 0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a vrl vrh 85 v dd a 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa 1 5 pa 1 4 pa 1 3 pd0 pd1 56 pb9 / / / / / / / / / / / / / / / / / / / / / / / / / / cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0 pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / nexpr nexps ss_b emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda pcs0_b / / / an9_a an8_a an7_a an6_a an5_a an4_a an3_a an2_a an1_a an0_a irq xirq clkout sin_b sout_b sck_b pcs1_b pcs5_b / / / / / / / / / / / / / / / / / / / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a 1. pd2 function not available on l49p mask set devices. 2 on l49p mask set devices, pb11 / pcs2_b is bonded out on pin 57. pd2 (1) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 44 4.4 mac7122 pin diagram figure 18. pin assignments for mac7122 in 112-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 mac7122 112 lqfp 28 pf7 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa 7 pa 8 pa 9 pa 1 0 pa 1 1 pa 1 2 pd5 pc15 v dd x v ss x pd4 pd3 pd2 pb15 pb14 pb13 pb12 57 pb10 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 pg3 pg2 pg1 pg0 pg15 pg14 pa 0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a vrl vrh 85 v dd a 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa 1 5 pa 1 4 pa 1 3 pd0 pd1 56 pb9 / / / / / / / / / / / / / / / / / / / / / / cntx_a cnrx_a cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / nexpr nexps ss_b emios6 emios5 emios4 emios3 emios2 emios1 emios0 modb moda pcs0_b / / / an9_a an8_a an7_a an6_a an5_a an4_a an3_a an2_a an1_a an0_a irq xirq sin_b sout_b sck_b pcs1_b pcs5_b / / / / / / / / / / / / / clkout / / / / / / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 45 4.5 mac7101 / mac7106 pin diagram figure 19. pin assignments for mac7101 / mac7106 in 144-pin lqfp mac7101 / mac7106 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 pc0 pc1 pc2 pc3 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pc4 pc5 pc6 pc7 pf11 pf10 pf9 pf8 pf7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 lqfp cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / / / / / / / / / / / / / / / pf6 pf5 pf4 pf3 pf2 pf1 pf0 pc8 pc9 pc10 pc11 pg12 pg13 pa 1 5 pa 1 4 pa 1 3 pd11 pd12 pd0 pd1 pb9 reset v ss x v dd x v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test v ss x v dd x emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda pcs0_b nexpr nexps ss_b / / / / / / / / / / / / / / / ph10 pe9 ph9 pe8 ph8 pe7 ph7 pe6 ph6 pe5 ph5 pe4 ph4 pe3 ph3 pe2 ph2 pe1 ph1 pe0 ph0 v dd x v ss x pd15 pd14 pd13 pd4 pd3 v ss x pb15 pb14 pb13 pb12 pb11 pb10 / an10_b / an9_a / an9_b / an8_a / an8_b / an7_a / an7_b / an6_a / an6_b / an5_a / an5_b / an4_a / an4_b / an3_a / an3_b / an2_a / an2_b / an1_a / an1_b / an0_a / an0_b / irq / xirq / clkout / sin_b / sout_b / sck_b / pcs1_b / pcs2_b / pcs5_b / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / mcko / evto / evti / mdo0 / mdo1 / mseo / rdy tms tck tdo tdi v dd 2.5 v ss 2.5 v ss x v dd x / an15_a / an15_b / an14_a / an14_b / an13_a / an13_b / an12_a / an12_b / an11_a / an11_b / an10_a v ss a vrl vrh v dd a pg3 pg2 pg1 pg0 pg15 pg14 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pe15 ph15 pe14 ph14 pe13 ph13 pe12 ph12 pe11 ph11 pe10 1. pd2 function not available on l49p mask set devices. pd2 (1) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 46 4.6 mac7111 / mac7116 pin diagram figure 20. pin assignments for mac7111 / mac7116 in 144-pin lqfp mac7111 / mac7116 pf6 pf5 pf4 pf3 pf2 pf1 pf0 pc8 pc9 pc10 pc11 pg12 pg13 pa 1 5 pa 1 4 pa 1 3 pd11 pd12 pd0 pd1 pb9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa 7 pa 8 pa 9 pa 1 0 pa 1 1 pa 1 2 pd5 pc15 pc14 pc13 pc12 v dd x v ss x pd15 pd14 pd13 pd4 pd3 ta / as pb15 pb14 pb13 pb12 pb11 pb10 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 pc0 pc1 pc2 pc3 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pc4 pc5 pc6 pc7 pf11 pf10 pf9 pf8 pf7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 reset v ss x v dd x v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test v ss x v dd x 144 lqfp / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / data0 / data1 / data2 / data3 / data4 / data5 / data6 tms tck tdo tdi v dd 2.5 v ss 2.5 v ss x v dd x / addr21 / addr20 / addr19 / addr18 / addr17 / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a v ss a vrl vrh v dd a cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b addr0 addr1 addr2 addr3 sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 addr4 addr5 addr6 addr7 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 addr8 addr9 addr10 addr11 rxd_d txd_d data15 data14 data13 oe cs2 bs0 bs1 pcs0_b nexpr nexps modb moda ss_b / / / / / / / / / / / / / / / / / / / / / / / / / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / data7 / data8 / data9 / data10 / data11 / data12 / addr16 / addr15 / addr14 / addr13 / addr12 / r/w / cs0 / cs1 / irq / xirq / clkout / sin_b / sout_b / sck_b / pcs1_b / pcs2_b / pcs5_b / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b pg3 pg2 pg1 pg0 pg15 pg14 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 / mcko / evto / evti / mdo0 / mdo1 / mseo / rdy 1. pd2 function not available on l49p mask set devices. pd2 (1) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 47 4.7 mac7112 pin diagram figure 21. pin assignments for mac7112 in 144-pin lqfp pf6 pf5 pf4 pf3 pf2 pf1 pf0 pc8 pc9 pc10 pc11 pg12 pg13 pa 1 5 pa 1 4 pa 1 3 pd11 pd12 pd0 pd1 pb9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa 7 pa 8 pa 9 pa 1 0 pa 1 1 pa 1 2 pd5 pc15 pc14 pc13 pc12 v dd x v ss x pd15 pd14 pd13 pd4 pd3 pd2 v ss x pb15 pb14 pb13 pb12 pb11 pb10 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 pc0 pc1 pc2 pc3 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pc4 pc5 pc6 pc7 pf11 pf10 pf9 pf8 pf7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 reset v ss x v dd x v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test v ss x v dd x mac7112 144 lqfp / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / mcko / evto / evti / mdo0 / mdo1 / mseo / rdy tms tck tdo tdi v dd 2.5 v ss 2.5 v ss x v dd x / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a v ss a vrl vrh v dd a cntx_a cnrx_a cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / / / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 modb moda pcs0_b nexpr nexps ss_b / / / / / / / / / / / / / / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / irq / xirq / clkout / sin_b / sout_b / sck_b / pcs1_b / pcs2_b / pcs5_b / rdy' / mseo' / mdo1' / mdo0' / evti' / evto' / mcko' / xclks / pcss_b pg3 pg2 pg1 pg0 pg15 pg14 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary device pin assignments freescale semiconductor 48 4.8 mac7131 pin diagram 12345678910111213141516 a v ss xv ss x pg0 pg14 pa2 pa5 tck tdi pe15 pe14 ph14 pe12 ph11 v rl v rh v dd a b v ss xv ss x pg2 pg15 pa0 pa4 tms tdo pd9 ph15 pe13 ph12 pe10 ph9 v dd aph8 c pg5 pg3 v ss x pg1 pa1 pa3 pa6 v dd 2.5 v dd x pd6 ph13 pe11 v dd a pe8 pe7 ph7 d pg9 pg8 pg4 v ss xv ss xv ss 2.5 v ss 2.5 pd10 pd8 pd7 v ss av ss a ph10 pe9 pe6 ph6 e pg6 pg11 pg10 v ss x pe4 pe5 ph5 ph4 f pc0 pg7 pc1 v ss x pe2 pe3 ph3 ph2 g pb0 pc2 pc3 v ss xv ss xv ss xv ss xv ss x ph0 ph1 pe1 pe0 h pb3 pb2 pb1 v dd xv ss xv ss xv ss xv ss x pa8 pa9 pa7 pa10 j pb5 pb6 pb4 v ss xv ss xv ss xv ss xv ss x pd5 pa12 pa11 pc15 k pb7 pb8 pf15 v ss xv ss xv ss xv ss xv ss x pc13 pc12 pc14 v dd x l pf14 pf13 pc4 v ss x pd13 pd14 pd15 pd4 m pf12 pc5 pc6 v ss xv ss x ta /as (1) pd3 pd2 (1) n pf11 pf10 pc7 v ss xv ss rv ss rv ss 2.5 v ss 2.5 v ss pll v ss pll v ss xv ss xv ss x pb11 pb14 pb15 p pf9 pf8 v ss xpf5 pc8pc10v dd xv dd 2.5 v dd rv dd x pa15 pd11 pd12 v ss x pb12 pb13 r pf7 v ss x pf6 pf3 pf1 pc9 pg12 pg13 v ss xv ss x test pa13 pd1 pb10 v ss xv ss x t v ss xv ss x pf4 pf2 pf0 pc11 reset v dd pll xfc extal xtal pa14 pd0 pb9 v ss xv ss x 1. as and pd2 functions not available on l49p mask set devices. figure 22. pin assignments for mac7131 in 208-pin map bga because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
device pin assignments mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 49 4.9 mac7136 pin diagram 12345678910111213141516 a v ss xv ss x pg0 pg14 pa2 pa5 tck tdi pe15 pe14 ph14 pe12 ph11 v rl v rh v dd a b v ss xv ss x pg2 pg15 pa0 pa4 tms tdo pd9 ph15 pe13 ph12 pe10 ph9 v dd aph8 c pg5 pg3 pi0 pg1 pa1 pa3 pa6 v dd 2.5 v dd x pd6 ph13 pe11 v dd a pe8 pe7 ph7 d pg9 pg8 pg4 pi2 pi1 v ss 2.5 v ss 2.5 pd10 pd8 pd7 v ss av ss a ph10 pe9 pe6 ph6 e pg6 pg11 pg10 pi3 pe4 pe5 ph5 ph4 f pc0 pg7 pc1 v ss x pe2 pe3 ph3 ph2 g pb0 pc2 pc3 pi4 v ss xv ss xv ss xv ss x ph0 ph1 pe1 pe0 h pb3 pb2 pb1 v dd xv ss xv ss xv ss xv ss x pa8 pa9 pa7 pa10 j pb5 pb6 pb4 pi5 v ss xv ss xv ss xv ss x pd5 pa12 pa11 pc15 k pb7 pb8 pf15 pi6 v ss xv ss xv ss xv ss x pc13 pc12 pc14 v dd x l pf14 pf13 pc4 pi7 pd13 pd14 pd15 pd4 m pf12 pc5 pc6 v ss xv ss xta / as pd3 pd2 n pf11 pf10 pc7 pi8 v ss rv ss rv ss 2.5 v ss 2.5 v ss pll v ss pll pi12 pi13 pi14 pb11 pb14 pb15 p pf9 pf8 pi9 pf5 pc8 pc10 v dd xv dd 2.5 v dd rv dd x pa15 pd11 pd12 pi15 pb12 pb13 r pf7 pi10 pf6 pf3 pf1 pc9 pg12 pg13 v ss xv ss x test pa13 pd1 pb10 pi11 v ss x t v ss xv ss x pf4 pf2 pf0 pc11 reset v dd pll xfc extal xtal pa14 pd0 pb9 v ss xv ss x figure 23. pin assignments for mac7136 in 208-pin map bga because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary mechanical information freescale semiconductor 50 5 mechanical information as indicated in table 2 , mac7100 family devices are available in several packages. please refer to the freescale.com web site for the most up-to-date package avai lability and mechanical information. the table below lists available package identifiers a nd freescale document num bers for reference. table 39. package identifiers and mechanical specifications package type case identifier mechanical specification document 100-lead lqfp 983-02 98ass23308w 112-lead lqfp 987-02 98ass23330w 144-lead lqfp 918-03 98ass23177w 208-lead map bga 1159a-01 98ars23882w because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mechanical in formation mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 51 revision history revision history version no. release date description of changes page numbers v0.1 29-oct-03 first public customer release (preliminary). v1.0 14-sep-04 general ? converted to freescale identity, with blue cross-reference highlights for enhanced pdf navigation, and miscellaneous updates for presentation consistency. ? the order of section 3.5 and section 3.6 were reversed for better content flow. this has caused specification numbering to change as detailed below. note: content consolidation and reorganization has resulted in the following table and specification number changes (the first spec number of each table is shown): 7 , 8 section 2, ?ordering information? ? added ta b l e 1 , mask set information ? updated ta bl e 2 with expanded port pin counts, mac71 x 2 and mac71x 6 family members ? pin assignment changes for mask set l47w devices: ?in table 37 , pb10 / pcs5_b / pcss_b changed to pin 57, footnote for l49p 2 3 36 table title rev. 1.0 rev. 0.1 5.0 v i/o characteristics table 8 d1a table 15 f1 3.3 v i/o characteristics table 9 e1a table 16 g1 section 3.6, ?power dissipation and thermal characteristics? table 10 to table 14 table 7 to table 11 mac71x1/6 device supply current characteristics ? 40 mhz table 15 f1 table 12 d1a mac71x1/6 device supply current characteristics ? 50 mhz table 16 g1 n/a vreg operating conditions table 17 h1 table 13 e1 vreg recommended load capacitances table 18 table 14 oscillator characteristics table 19 j1a table 17 h1a pll characteristics table 20 k1 table 18 j1 crystal monitor time-outs table 21 table 19 crg maximum clock quality check timings table 22 table 20 crg startup characteristics table 23 l1 table 21 k1 external bus input timing specifications table 24 m1 table 22 l1 external bus output timing specifications table 25 m6a table 23 l6a atd operating characteristics in 5.0 v range table 26 n1 table 24 m1 atd operating characteristics in 3.3 v range table 27 p1 table 25 n1 atd electrical characteristics table 28 q1 table 26 p1 atd conversion performance in 5.0 v range table 29 r1 table 27 q1 atd conversion performance in 3.3 v range table 30 s1 table 28 r1 atd electrical characteristics (operating) n/a table 29 s1 atd performance specifications n/a table 30 t1 atd timing specifications n/a table 31 u1 atd external trigger timing specifications table 31 t1 table 32 v1 spi master mode timing characteristics table 32 u1a table 33 w1a spi slave mode timing characteristics table 33 v1a table 34 x1a flexcan wake-up pulse characteristics table 34 w1 table 35 y1 cfm timing characteristics table 35 x1 table 36 z1 nvm reliability characteristics table 36 x9b table 37 z10 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary mechanical information freescale semiconductor 52 v1.0 14-sep-04 (continued) section 3, ?electri cal characteristics? ? section 3.2, ?absolute maximum ratings? ? a1a renamed to v dd x ? a4 ?rating? changed to analog (from atd) ? a9 minimum changed to ?0.3 ? a12 maximum value removed, footnote reference added ? ta b l e 8 , ta b l e 9 footnotes added regarding v dd 5/v ss 5 ? section 3.4, ?operating conditions? ? c1 renamed to v dd x ? c4 added ( c5 to c11b renumbered) ? c8 maximum changed from 40 mhz to 50 mhz ? section 3.5, ?input/o utput characteristics? ? ta b l e 8 spec d4 updated (from tbd) ? ta b l e 9 spec e4 changed to 1 a to match d4 ? section 3.6, ?power dissipat ion and thermal characteristics? ? reworked equation 1 through equation 4 and supporting text ? section 3.6.1 and table 10 name changed from ?power dissipation...? ? section 3.7, ?power supply? ? added mac71 x 1 designation and footnotes to table 15 / table 16 ? ta b l e 1 5 designated for 40 mhz, and ? numerous tbd entries replaced with values ? run supply current collapsed from fifteen spec items to one ? removed separate core/regulator/pins specs for run/pseudo stop/stop modes ? f1 and f3 descriptions changed ? f1 , f2 , f3 and f4 values updated ? ta b l e 1 6 added for 50 mhz specifications ? ta b l e 1 7 , deleted i reg spec (regulator current in reduced power, shutdown modes) ? ta b l e 1 8 , v dd 2.5 load capacitance typical changed, with clarif ication footnote ? section 3.8, ?clock and reset generator? ? ta b l e 1 9 updates ? changed specs j1b and j6 maximum from 40 mhz to 50 mhz ? reversed polarity of xclks reference in footnote ( 3 ) ? j1b maximum changed to 40 mhz ?v dcbias removed ? added footnote to define t fsys as 1 f sys for use elsewhere in the document ? updated section 3.8.2, ?pll f ilter characteristics? ? ta b l e 2 0 updates ? changed spec k3 maximum from 40 mhz to 50 mhz ? added footnote to define t fsys as 1 f sys for use elsewhere in the document ? ta b l e 2 3 updates ?removed v porr and v pora , as they duplicated h6 ?removed t wrs ? section 3.9, ?external bus timing? ? ta b l e 2 4 updates ? m1 minimum changed from 25 ns to 20 ns ( figure 6 also updated) ? reworded footnote ( 1 ) ? added footnote ( 2 ) to define t cyc as 1 clkout ? ta b l e 2 5 updates ? added footnote ( 1 ) ? consolidated previous notes into footnote ( 2 ), ( figure 7 , figure 8 also updated) 4 4 5 5 7 , 8 6 6 6 7 8 9 10 12 12 13 14 15 16 18 19 20 21 revision hist ory (continued) version no. release date description of changes page numbers because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mechanical in formation mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 53 v1.0 14-sep-04 (continued) section 3, ?electri cal characteristics? (continued) ? section 3.10, ?analog-to-digital converter? ? rev. 0.1 redundant and su perfluous content deleted ? section 3.10.3, ?atd electrical specificat ions,? (included table 29 and table 30) ? table 31, ?atd performance specifications? (redundant with v0.1 table 27 and table 28, now ta bl e 2 9 and table 30 ) ? ta b l e 2 6 updates ? deleted previous spec m6 ? changed spec n7 and n8 values ? ta b l e 2 7 updates ? deleted previous spec n6 ? changed spec p7 and p8 values ? changed spec p2 and footnote ( 1 ) to specify 3.15 v ? ta b l e 2 8 updates ? changed spec q2 parameter classification from t to c and 10 pf and 22 pf values moved from maximum to typical ? ta b l e 2 9 updates ? operating conditions v dd a minimum changed to 4.5 v ?v ref description moved from ?conditions? header to new footnote ( 1 ) ? ta b l e 3 0 updates ? operating conditions v dd a minimum changed to 3.15 v ?v ref description moved from ?conditions? header to new footnote ( 1 ) ? ta b l e 3 1 updates ? spec t1 description clarified, max removed, min added with footnote ? spec t2 modified to show both edge- and level-sensitive modes ? figure 10 modified to remove ?max frequency? label and clearly separate edge- and level-sensitive mode timing examples ? section 3.11, ?serial peripheral interface? ? ta b l e 3 2 updates ? changed specs u1a, u1b and u4 to use f ips and t ips for clarity and consistency with mac7100rm ? changed u1a max to ? and u1b min to 2 to account for the dbr bit ? ta b l e 3 3 updates ? changed specs v1a , v1b , v2 , v3 , v4 , v7 , v8 to use f ips and t ips for clarity and consistency with mac7100rm ? changed v1a max to ? and v1b min to 2 to account for the dbr bit ? section 3.13, ?common flash module? ? significant rework to match mac7100rm clock naming, references and timing calculations for clarity and consistency ? changed x1 maximum from 40 mhz to 50 mhz ( table 35 ) 24 24 24 25 26 26 28 28 29 29 32 to 35 34 revision hist ory (continued) version no. release date description of changes page numbers because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary mechanical information freescale semiconductor 54 v1.0 14-sep-04 (continued) section 4, ?device pin assignments? ? ta b l e 3 7 and ta b l e 3 8 added ? added pd2 label / footnote to figure 15 , figure 17 , figure 19 , figure 20 and figure 22 ? section 4.2, ?mac7142 pin diagram? / figure 16 added ? section 4.3, ?mac7121 / mac7126 pin diagram? / figure 17 updated ? pb10 / pcs5_b / pcss_b bonded out on pin 57, footnote for l49p ? added mac71 x 6 device information ? section 4.4, ?mac7122 pin diagram? / figure 18 added ? section 4.5, ?mac7101 / mac7106 pin diagram? / figure 19 updated ? added mac71 x 6 device information ? section 4.6, ?mac7111 / mac7116 pin diagram? / figure 20 updated ? added as to ta pin ? added mac71 x 6 device information ? section 4.7, ?mac7112 pin diagram? / figure 21 added ? section 4.8, ?mac7131 pin diagram? / figure 22 corrected, updated ? changed pins c8 & p8 from v ss 2.5 to v dd 2.5 ? changed pin t8 from v ss pll to v dd pll ? added as to ta pin ? section 4.9, ?mac7136 pin diagram? / figure 23 added 36 , 40 41 , 43 , 45 , 46 , 48 42 43 44 45 46 47 48 49 v1.1 1-dec-04 section 3, ?electri cal characteristics? ? section 3.7, ?power supply? ? ta b l e 1 5 spec f4 ?40 c and 25 c max value changed ? ta b l e 1 6 spec g4 ?40 c and 25 c max value changed ? section 3.8, ?clock and reset generator? ? ta b l e 1 9 spec j3 typical tbd entry replaced with value ? ta b l e 2 0 specs k15 and k16 maximum tbd entries replaced with values 12 12 15 18 v1.1.1 3-dec-04 section 3, ?electri cal characteristics? ? section 3.7, ?power supply? ? ta b l e 1 5 spec f3 ?40 c, 25 c and 125 c typ and max values and unit changed ? ta b l e 1 6 spec g3 ?40 c, 25 c and 125 c typ and max value and unit changed 12 12 v1.2 10-feb--06 section 1, ?overview? ? moved 71x6 device numbers from footnote to ?covered? list section 2, ?ordering information? ? added af, ag and vm package identifiers to figure 1 ? added 1l38y to ta b l e 1 section 3, ?electri cal characteristics? ? replaced tbd values in table 15 and ta b l e 1 6 with final qualification data, changed table titles and footnotes to reflect 71x6 inclusion. section 5, ?mechanical information? ? removed obsolete package diagrams, replaced with document ids available on web site. 1 2 2 12 50 revision hist ory (continued) version no. release date description of changes page numbers because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100 microcontroller family ha rdware specifications, rev. 1.2 preliminary freescale semiconductor 55 this page intentionally left blank. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages
mac7100ec rev. 1.2, 02/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. all other product or service names are the property of their respective owners. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to www.freescale.com/epp . ? freescale semiconductor, inc. 2004-2006. all rights reserved. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010:mac7131 products in 208 mapbga packages

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